Quick Start   About This Project   How to Use

Quick Start

In order to execute your program using this simulator, please follow the following steps:

1. Load source files, including assembly code and data file. You have the following two options:
• To choose your source code and data file from the computer you are running this simulator on, click on the "Load Program" button on the bottom right.
• To edit your source code and data file for execution, click on the "Edit Program" button on the bottom right. A new editable text field will show up, you can edit your source code and data file in that field.
2. Choose configurations for your execution, you have the following options:
• Choose "Data Forwarding On/Off" by clicking on the top button on the right.
• Choose "Delayed Branch On/Off" by clicking the second top button on the right.
• Choose "Delayed Load On/Off" by clicking the third top button on the right.
• Choose "Cache Write Back/Through" by clicking the fourth top button on the right.
• Choose "Memory Interleave On/Off" by clicking the fifth top button on the right.
• Choose "Branch Target Buffer On/Off" by clicking the six top button on the right.
• Choose cache memory size by tuning the scale bar below the cache memory.
3. Execute your program. By clicking on the "Single Cycle/Continuous" button on the bottom right, you can execute your program either stepwise or continuously.
4. You can stop the execution any time by clicking on the "Reset" button.

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About This Project

This project is to design and implement a simulated pipeline for the instruction execution cycle of DLX for all (both floating and non-floating point) operations. A Graphical User Interface (GUI) needs to be developed for the pipeline such that the pipeline operations and changes to the state of the machine can be observed on the screen when sample applications are "executed".

One can change cache size (0, 4 or 8 words), select write back or write through option for cache, turn on/off data forwarding, select delayed branch option, turn on/off memory interleaving, and turn on/off branch target buffer.

1. It should simulate a true DLX architecture by keeping track of the updates to registers, latches, cache, data memory, and branch target buffer.
2. It must be able to handle data forwarding, delayed branches (should support both taken/not-taken), and delayed loads.
3. Assume each pipeline state takes one (1) clock cycle, including an instruction/data access from cache.
4. Assume each pipeline stage takes one (1) cycle, including an instruction/data access from cache.

1. Non-interleaved memory accesses take four (6) clock cycles.
2. One word interleaved memory accesses take one (1) clock cycle to send the address, four (4) clock cycles to access a memory block, and one (1) clock cycle to read/write the data.
3. Cache set associative organization with two blocks per set.
4. Cache size should be configurable to be set to 0 words, 4 words and 8 words.
5. Cache write policy should be configurable to be either write back or write through.

The GUI must continuously (dynamic updates during an execution run) display the following items at the END of each cycle:

1. A pipeline cycle number.
2. Current instruction pointer.
3. The instruction executing in each pipeline stage.
4. Insertion of a stall/NOP is signaled by a red background color for each stage of the pipeline that the NOP goes through.
5. The contents of the registers.
6. The contents of the instruction memory.
7. The contents of the data memory.
8. The contents of the cache.
9. An option button that will open a window to show branch target buffer when clicked.
10. An option button to run the simulator in "Continuous Mode". In this mode, each pipeline cycle should be programmed to take 2 seconds.
11. An option button to run the simulator in "Step Mode". In this mode, each pipeline cycle advances by another click of the "Step" button.
12. A "Load/Edit" button that gives the user a choice of programs (and associated data memory contents) to load into the instruction and data memories.
13. An option button/menu for setting simulator configuration parameters.

1. The pipeline must handle the entire DLX instruction set in the text.
2. All data and addresses are in base 10.
3. The integer data values range from 0 to 99 (note that all data and instructions are 1 word long).
4. Only single precision floating-point data values have to be supported.
5. Instruction memory capacity is 32 words (0 to 31).
6. Data memory capacity is 64 words (0 to 63) in two banks (when interleaving is turned on) that should be interleaved (interleave bank determined by least significant bit).
7. Cache may vary in size from 0, 4 or 8 words (configurable).
8. There are only 16 registers (R0 to R15) - R0 is always 0, R14 is the stack pointer and R15 holds the return address.
9. The size of branch target buffer is 4.
10. Assume programs are specified in an ASCII file with one instruction per line.
11. Assume the data memory content (at the beginning of the program execution) is specified in an ASCII file in sequential order, one data item per line (i.e., first data item on the first line is for location 0, second data item on the second line is for location 1, etc.), all unspecified locations contain 0. The following are three sample input files, each with an instruction file and data file.

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How to Use

The GUI can be divided into three big components, the display of the pipeline, which is on the top left of the GUI; the display of the internal storage, including data memory, instruction memory, cache, registers, and branch target buffer, which is on the bottom left of the GUI; and the functional button for execution of the application, which is on the right of the GUI. The displays are in decimal format and wordwise except for the pipeline stages and instruction memory, which are displayed as assembly code.

The DLX pipeline has five stages (i.e., IF (Instruction Fetch), ID (Instruction Decoding), EX (Execution), MEM (Memory), and WB (Write Back)), and four latches (i.e., IF/ID, ID/EX, EX/MEM, and MEM/WB). The contents of each pipeline stage are displayed as text fields below the corresponding stage. The content of a latch can be displayed by clicking on the corresponding latch bar, e.g., clicking on the MEM/WB bar will result in a display of the contents of MEM/WB latch.

The data memory is displayed on the bottom left of the GUI. The size of the data memory is 64 words.

The instruction memory is on the right of the data memory. The size of the instruction memory is 32 words.

Cache memory is on the right of the instruction memory. The cache memory is configurable. Its size can be adjusted to either 0, 4, or 8 words by tuning the scale bar below it.

The registers are displayed on the right of the cache memory. There are 16 registers (R0 to R15) - R0 always contains 0 and is read only; R14 is the stack pointer and R15 holds the return address for procedure calls.

The branch target buffer will be displayed on the bottom right, if it is turned on. Its size is 4 words.

The program counter (PC) is displayed in the pipeline figure in the IF stage.

The execution cycle number is displayed above the branch target buffer.

In order to execute your program using this simulator, please follow the following steps:

1. Load source files, including assembly code and data file. Your program should have the format as described in the "Project Description". You have the following two options:
• To choose your source code and data file from the computer you are running this simulator on, click on the "Load Program" button on the bottom right, then you can browse on your computer to locate the program you want to execute.
• To edit your source code and data file for execution, click on the "Edit Program" button on the bottom right. A new editable text field will show up, you can edit your source code and data file in that field.
2. Choose configurations for your execution, you have the following options:
• Choose "Data Forwarding On/Off" by clicking on the top button on the right. When the button is up, the "data forwarding" is off; otherwise, it is on.
• Choose "Delayed Branch On/Off" by clicking the second top button on the right. When the button is up, the "delayed branch" functionality is off; otherwise, it is on.
• Choose "Delayed Load On/Off" by clicking the third top button on the right. When the button is up, the "delayed load" functionality is off; otherwise, it is on
• Choose "Cache Write Back/Through" by clicking the fourth top button on the right. When the button is up, the "cache write through" is used; otherwise, "cache write back" is used. (Note: This depends on size of cache memory being non-zero)
• Choose "Memory Interleave On/Off" by clicking the fifth top button on the right. When the button is up, the "memory interleaving" is off; otherwise, it is on.
• Choose "Branch Target Buffer On/Off" by clicking the six top button on the right. When the button is up, the "branch target buffer" is off; otherwise, it is on, and a branch target buffer of 4 words will appear at the bottom right.
• Choose the cache memory size by tuning the scale bar in the middle bottom of the GUI. The size can be set to either 0, 4, or 8.
3. Execute your program. By clicking on the "Single Cycle/Continuous" button on the bottom right, you can execute your program either stepwise or continuously. When the button is up, you program will execute in a stepwise mode; otherwise, it will execute continuously. In the stepwise execution mode, you can execute a single pipeline stage by clicking on the "Execute a Single Cycle" button once; In the continuous mode, the program will execute continuously, the execution result will update every two seconds When executing your program, you can observe the content of each pipeline stage, contents of data memory, instruction memory, cache memory (if its size is not set to 0), registers, as well as the contents of the program counter (PC) and the execution cycle number.
4. You can stop the execution any time by clicking on the "Reset" button, and then start executing a new program or quit.

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